1 file number 3598.3 caution: these devices are sensitive to electrostatic discharge; follow proper esd handling procedures. pspice?is a registered trademark of microsim corporation. http://www.intersil.com or 407-727-9207 | copyright intersil corporation 1999 RFD7N10LE, RFD7N10LEsm 7a, 100v, 0.300 ohm, n-channel, logic level, power mosfets these n-channel power mosfets are manufactured using a modern process. this process, which uses feature sizes approaching those of lsi integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers and emitter switches for bipolar transistors. this performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3v to 5v range, thereby facilitating true on-off power control directly from logic level (5v) integrated circuits. formerly developmental type ta49046. features 7a, 100v ? ds(on) = 0.300 ? temperature compensating pspice model can be driven directly from cmos, nmos, ttl circuits peak current vs pulse width curve uis rating curve 175 o c operating temperature related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging ordering information part number package brand RFD7N10LE to-251aa 7n10l RFD7N10LEsm to-252aa 7n10le note: when ordering, use the entire part number. add suffix 9a to ob- tain the to-252aa variant in the tape and reel, i.e., RFD7N10LEsm9a. d g s jedec to-251aa jedec to-252aa source drain gate drain (flange) gate source drain (flange) data sheet october 1999
2 absolute maximum ratings t c = 25 o c, unless otherwise speci?d RFD7N10LE, RFD7N10LEsm units drain to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 100 v drain to gate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 100 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs +10, -8 v drain current continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 7 refer to peak current curve a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as refer to uis curve power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 0.318 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v 100 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a1-3v zero gate voltage drain current i dss v ds = 95v, v gs = 0v - - 1 a v ds = 90v, v gs = 0v, t c = 150 o c - - 250 a gate to source leakage current i gss v gs = +10, -8v - - 10 a on resistance r ds(on) i d = 7a, v gs = 5v - - 0.300 ? turn-on time t on v dd = 50v, i d = 7a r l = 7.1 ? , v gs = 5v r gs = 2.5 ? - - 110 ns turn-on delay time t d(on) -10- ns rise time t r -65- ns turn-off delay time t d(off) -23- ns fall time t f -18- ns turn-off time t off - - 60 ns total gate charge q g(tot) v gs = 0 to 10v v dd = 80v i d = 7a, r l = 11.4 ? - 125 150 nc gate charge at 5v q g(5) v gs = 0 to 5v - 67 80 nc threshold gate charge q g(th) v gs = 0 to 1v - 3.7 4.5 nc input capacitance c iss v ds = 25v, v gs = 0v f = 1mhz - 360 - pf output capacitance c oss -70- pf reverse transfer capacitance c rss -20- pf thermal resistance junction to case r jc - - 3.15 o c/w thermal resistance junction to ambient r ja to-251 and to-252 package - - 100 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 7a - - 1.5 v reverse recovery time t rr i sd = 7a, di sd /dt = 100a/ s - - 130 ns RFD7N10LE, RFD7N10LEsm
3 typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t c , case temperature ( o c) 25 50 75 100 125 150 175 0 power dissipation multiplier 0 0 0.2 0.4 0.6 0.8 1.0 1.2 t c , case temperature ( o c) i d , drain current (a) 8 4 2 0 25 50 75 100 125 150 175 6 t, rectangular pulse duration (s) 10 -5 10 -3 10 -2 10 -1 10 0 10 1 10 -4 z jc, normalized thermal impedance 0.01 0.1 1 single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z jc x r jc + t c p dm t 1 t 2 0.01 0.5 0.2 0.1 0.05 0.02 v ds , drain to source voltage (v) 1 10 200 i d , drain current (a) 0.1 1 20 10 100 s 1ms 10ms v dss max = 100v operation in this area may be limited by r ds(on) 14 t c = 25 o c t j = max rated v gs = 5v for temperatures above 25 o c derate peak current as follows: i = i 25 ( ) 175 - t c 150 transconductance may limit current in this region t, pulse width (ms) 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 i dm , peak current (a) 20 10 5 14 RFD7N10LE, RFD7N10LEsm
4 figure 6. unclamped inductive switching figure 7. saturation characteristics figure 8. transfer characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature typical performance curves unless otherwise speci?d (continued) t av , time in avalanche (ms) 0.001 0.01 0.1 1 1 10 14 20 t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] starting t j = 150 o c starting t j = 25 o c i as , avalanche current (a) v ds , drain to source voltage (v) i d , drain current (a) 0 5 10 15 0 1.5 3.0 4.5 6.0 7.5 v gs = 3v v gs = 4v v gs = 4.5v v gs = 10v v gs = 5v pulse duration = 80 s t c = 25 o c duty cycle = 0.5% max 25 o c v gs , gate to source voltage (v) 0 34567 1 0 5 10 15 i d , drain current (a) -55 o c 2 175 o c v dd = 15v pulse duration = 80 s duty cycle = 0.5% max t j , junction temperature ( o c) normalized on resistance 0 0.5 1.0 1.5 2.0 2.5 3.0 -80 -40 04080 120 160 200 pulse duration = 80 s v gs = 5v, i d = 7a duty cycle = 0.5% max t j , junction temperature ( o c) -80 -40 04080 120 200 160 0 0.5 1.0 1.5 2.0 normalized gate v gs = v ds ,i d = 250 a threshold voltage 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 normalized drain to source breakdown voltage t j , junction temperature ( o c) i d = 250 a RFD7N10LE, RFD7N10LEsm
5 figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. normalized switching waveforms for constant gate current test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. resistive switching test circuit figure 17. resistive switching waveforms typical performance curves unless otherwise speci?d (continued) 600 400 200 0 0 510152025 c, capacitance (pf) v ds , drain to source voltage (v) c iss c oss c rss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 100 75 50 25 0 20 i gref () i g act () --------------------- - t, time ( s) 80 i gref () i g act () --------------------- - 5.00 3.75 2.50 1.25 0 v ds , drain to source voltage (v) v gs , gate to source voltage (v) v dd = bv dss 0.75 bv dss 0.50 bv dss 0.25 bv dss r l = 14.28 ? i g(ref) = 0.24ma v gs = 5v 0.75 bv dss 0.50 bv dss 0.25 bv dss v dd = bv dss t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r gs dut + - v dd v ds v gs t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 RFD7N10LE, RFD7N10LEsm
6 pspice electrical model subckt RFD7N10LE 2 1 3; rev 6/2/93 ca 12 8 7.5e-10 cb 15 14 7.6e-10 cin 6 8 4.03e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 116.7 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 3.7e-9 lsource 3 7 3.4e-9 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 9.4e-2 rgate 9 20 3.3 rldrain 2 5 10 rlgate 1 9 37 rlsource 3 7 34 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 1.3e-2 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*17.3),3.5))} .model dbodymod d (is = 1.2e-12 rs = 1.2e-2 trs1 = 1.2e-3 trs2 = 1.03e-6 cjo = 6.7e-10 tt = 6.9e-8 m = 0.77) .model dbreakmod d (rs = 9.9e-1 trs1 = 1e-3 trs2 = -2e-5) .model dplcapmod d (cjo = 4.3e-10 is = 1e-30 m = 0.9 n = 10) .model mmedmod nmos (vto = 1.88 kp = 5 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 3.3) .model mstromod nmos (vto = 2.13 kp = 12.4 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.59 kp = 0.12 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 33 rs = 0.1) .model rbreakmod res (tc1 = 1.05e-3 tc2 = -5e-7) .model rdrainmod res (tc1 = 8.1e-3 tc2 = 2.4e-5) .model rslcmod res (tc1 = 3e-3 tc2 = 2e-6) .model rsourcemod res (tc1 = 1e-3 tc2 = 1e-6) .model rvthresmod res (tc1 = -1.5e-3 tc2 = -4.3e-6) .model rvtempmod res (tc1 = -1.6e-3 tc2 = 1.5e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.5 voff= -2.5) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.5 voff= -4.5) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.3 voff= 0.2) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0.2 voff= -0.3) .ends note: for further discussion of the pspice model consult a new pspice sub-circuit for the power mosfet featuring global temperature options; ieee power electronics specialist conference records 1991. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 RFD7N10LE, RFD7N10LEsm
7 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?ation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com sales of?e headquarters north america intersil corporation p. o. box 883, mail stop 53-204 melbourne, fl 32902 tel: (407) 724-7000 fax: (407) 724-7240 europe intersil sa mercure center 100, rue de la fusee 1130 brussels, belgium tel: (32) 2.724.2111 fax: (32) 2.724.22.05 asia intersil (taiwan) ltd. 7f-6, no. 101 fu hsing north road taipei, taiwan republic of china tel: (886) 2 2716 9310 fax: (886) 2 2715 3029 RFD7N10LE, RFD7N10LEsm
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